Design & Reuse
Catalog of SIP Cores
System on Chip design resources
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66 IP
51
1.0
ASIP-2
The FFT/IFFT/DCT engine is an application specific instruction set processor (ASIP) optimized for the implementation of Fourier and cosine transforms,...
52
0.0
N-Point FFT/IFFT
The Fast Fourier Transform (FFT) is an efficient algorithm for computing the Discrete Fourier Transform (DFT). This Intellectual Property core was des...
53
0.0
128-Point FFT/IFFT
The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware. It runs at the clock frequency four times higher than the...
54
0.0
Hardware NLM (Non-Local-Mean) Video Noise Reduction IP core
NLM (Non Local Mean) is a noise reduction algorithm wherein the value of each pixel is determined a rectangle of pixels around that pixel (a “center p...
55
0.0
Scalable 3D Graphics Accelerator
The logi3D graphics accelerator IP core is specifically designed for the new Xilinx Zynq-7000 All Programmable SoC. Designers can add attractive 3D gr...
56
0.0
Perspective Transformation and Lens Correction Image Processor
The logiVIEW Perspective Transformation and Lens Correction Image Processor IP core for video and imaging applications using single or multiple camera...
57
0.0
Wideband Digital Down Converter (Digital DDC)
The IPrium-Wideband-DDC IP core is full-featured wideband digital downconverter and includes complex digital mixer and digital decimation filter with ...
58
0.0
Digital filter with input sampling rate 2.56 MHz
The block consists of 4 low pass filters connected in serially. Decimation takes place during a filtration process after each stage. The total decim...
59
0.0
Bit Block Transfer 2D video accelerator
The logiBITBLT is 2D graphic accelerator or BitBlitter IP core from Xylon logicBRICKS™ IP library. BITBLT is an acronym that stands for Bit Block Tran...
60
0.0
Bitmap 2.5D Graphics Accelerator
The logiBMP is 2.5D graphics accelerator from Xylon logicBRICKS IP library, optimized for Xilinx FPGAs and designed to speed up graphics operations wi...
61
0.0
Power and Ground BondPads that include CC-100IP Digital and Switching Circuit Power Reduction Technology, Featuring 20% to 40% Total Dynamic Power Reduction
All electronic systems that use CMOS digital circuits generate EM noise and currents (overlap current) as an undesired byproduct of their function. T...
62
0.0
Multi Channel FIR Filter
Finite Impulse Response (FIR) filters are important building blocks in signal processing. beam processing, diffraction compensation, equalisation and...
63
0.0
GUNZIP / ZLIB / Inflate Data Decompression Core
ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standa...
64
0.0
LZ4 / Snappy Data Compression
LZ4SNP-C is a custom hardware implementation of a lossless data compression engine that complies with the LZ4 and Snappy compression standards. The co...
65
0.0
LZ4 / Snappy Data Decompression
LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms. The core receives ...
66
0.0
GZIP / ZLIB / Deflate Data Compression Core
ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB c...